/*
 * @Author: LVGRAPE
 * @LastEditors: LVGRAPE
 */
#include "drv_spi.h"
#include "si24r1.h"
spi_dev_t nrf_spi = {
    .cs_pin = NRF_CSN_PIN,
    .mode = RT_SPI_MODE_0 | RT_SPI_MSB,
    .data_width = 8,
    .max_hz = 10 * 1000 * 1000,
};
void hw_si24r1_write_reg(uint8_t addr, uint8_t cmd)
{
    addr |= SI24R1_CMD_W_REGISTER;
    spi_send_then_send(&nrf_spi, &addr, 1, &cmd, 1);
}
uint8_t hw_si24r1_read_reg(uint8_t addr)
{
    uint8_t ret;
    addr &= SI24R1_CMD_R_REGISTER;
    spi_send_then_receive(&nrf_spi, &addr, 1, &ret, 1);
    return ret;
}
void hw_si24r1_read_reg_buf(uint8_t addr, uint8_t *buf, uint8_t len)
{
    addr &= SI24R1_CMD_R_REGISTER;
    spi_send_then_receive(&nrf_spi, &addr, 1, buf, len);
}
void hw_si24rq_reg_write_buf(uint8_t addr, uint8_t *buf, uint8_t len)
{
    addr |= SI24R1_CMD_W_REGISTER;
    spi_send_then_send(&nrf_spi, &addr, 1, buf, len);
}
void hw_si24r1_fifo_write(uint8_t *buf, uint8_t len)
{
    uint8_t cmd = SI24R1_CMD_W_TX_PAYLOAD;
    spi_send_then_send(&nrf_spi, &cmd, 1, buf, len);
}
void hw_si24r1_write_ack_payload(uint8_t *buf, uint8_t len)
{
    uint8_t cmd = SI24R1_CMD_W_ACK_PAYLOAD;
    spi_send_then_send(&nrf_spi, &cmd, 1, buf, len);
}
void hw_si24r1_fifo_read(uint8_t *buf, uint8_t len)
{
    uint8_t cmd = SI24R1_CMD_R_RX_PAYLOAD;
    spi_send_then_receive(&nrf_spi, &cmd, 1, buf, len);
}
void hw_si24r1_fifo_flush(void)
{
    uint8_t cmd = SI24R1_CMD_FLUSH_TX;
    spi_send_then_send(&nrf_spi, &cmd, 1, 0, 0);
}
void hw_si24r1_fifo_clear(void)
{
    uint8_t cmd = SI24R1_CMD_FLUSH_RX;
    spi_send_then_send(&nrf_spi, &cmd, 1, 0, 0);
}
uint8_t hw_get_rx_payload_width(void)
{
    uint8_t ret;
    uint8_t cmd = SI24R1_CMD_R_RX_PL_WID;
    spi_send_then_receive(&nrf_spi, &cmd, 1, &ret, 1);
    return ret;
}
void hw_si24r1_tx_address(uint8_t *addr)
{
    uint8_t cmd = SI24R1_REG_TX_ADDR | SI24R1_CMD_W_REGISTER;
    spi_send_then_send(&nrf_spi, &cmd, 1, addr, 5);
}
void hw_si24r1_rx_address(uint8_t *addr)
{
    uint8_t cmd = SI24R1_REG_RX_ADDR_P0 | SI24R1_CMD_W_REGISTER;
    spi_send_then_send(&nrf_spi, &cmd, 1, addr, 5);
}
void hw_si24r1_set_ce(void)
{
    pin_write(SI24R1_CE_PIN, PIN_HIGH);
}
void hw_si24r1_clear_ce(void)
{
    pin_write(SI24R1_CE_PIN, PIN_LOW);
}
void hw_si24r1_shutdown(void)
{
    hw_si24r1_clear_ce();
    hw_si24r1_write_reg(SI24R1_REG_CONFIG, 0X00);
}
void hw_si24rr1_tx_mode(void)
{
    hw_si24r1_clear_ce();
    hw_si24r1_write_reg(SI24R1_REG_SETUP_AW, 0x03);   // 地址宽度配置为5字节
    hw_si24r1_write_reg(SI24R1_REG_SETUP_RETR, 0x4c); // 自动重发延时500us,5次
    hw_si24r1_write_reg(SI24R1_REG_DYNPD, 0X01);
    hw_si24r1_fifo_flush();
    hw_si24r1_fifo_clear();
    hw_si24r1_write_reg(SI24R1_REG_STATUS, CLEAR_RX_IRQ | CLEAR_TX_IRQ | CLEAR_MAX_RT_IRQ);
}
void hw_si24r1_clr_rxit(void)
{
    hw_si24r1_write_reg(SI24R1_REG_STATUS, CLEAR_RX_IRQ);
}
void hw_si24r1_clr_txit(void)
{
    hw_si24r1_write_reg(SI24R1_REG_STATUS, CLEAR_TX_IRQ);
}
void hw_si24r1_clr_maxit(void)
{
    hw_si24r1_write_reg(SI24R1_REG_STATUS, CLEAR_TX_IRQ);
}
void hw_si24r1_nrf_power(uint8_t baudrate, uint8_t tx_power)
{
#define __1Mbps 0X00
#define __2Mbps 0X28
#define __250kbps 0X20
#define __7dBm 7
#define __4dBm 6
#define __3dBm 5
#define __1dBm 4
#define __0dBm 3
#define __N4dBm 2
#define __N6dBm 1
#define __N12dBm 0
    const uint8_t bps[3] = {__1Mbps, __2Mbps, __250kbps};
    if (baudrate >= 3)
        return;

    // CE = 0;
    hw_si24r1_clear_ce();
    hw_si24r1_write_reg(SI24R1_REG_RF_SETUP, bps[baudrate] | (tx_power & 0x07)); // 0db 修正之前注释错误
    // CE = 1;
    hw_si24r1_set_ce();
}
void hw_si24r1_rx_payload_size(uint8_t size)
{
    hw_si24r1_clear_ce();
    hw_si24r1_write_reg(SI24R1_REG_RX_PW_P0, size);
    hw_si24r1_set_ce();
}
void hw_si24r1_rf_channel(uint8_t channel)
{
    hw_si24r1_clear_ce();
    hw_si24r1_write_reg(SI24R1_REG_RF_CH, channel);
    hw_si24r1_set_ce();
}
uint8_t hw_si24r1_test(void)
{
    // uint8_t addr,cmd;
    // uint8_t reset_err = 0;
    uint8_t NRF_error = 0;
    // uint8_t tx_buff[1];
    // // CE = 0;
    // // SCK = 0;

    // // addr = 0x20;
    // // cmd = 0x0a;
    // // spi_send_then_send(&nrf_spi, 0, 0, 0, 0);
    // // // CSN = 0;
    // // // if (SPI(0x20) != 0x0e) { reset_err = 1;NRF_error |= 0x01; }//MISO bad
    // // // SPI(0x0a);
    // // // CSN = 1;

    // // CSN = 0;
    // // SPI(0x00);
    // // if (SPI(0x00) != 0x0a) { NRF_error |= 0x02; }//MOSI bad
    // // CSN = 1;

    // hw_si24r1_write_reg(0x01, 0x00);
    // hw_si24r1_write_reg(0x04, 0x00);
    // hw_si24r1_write_reg(0x11, 1);

    // hw_si24r1_fifo_write(tx_buff, 1);

    // // CE = 1;
    // hw_si24r1_set_ce();
    // rt_thread_delay(2);//init transimit

    // // CSN = 0;
    // // if (SPI(0x00) != 0x2e) { NRF_error |= 0x04; }//CE bad
    // // CSN = 1;

    // if (pin_read(SI24R1_IRQ_PIN) == PIN_HIGH)NRF_error |= 0x08;	//IRQ bad

    // hw_si24r1_write_reg(0x07, 0x20);	//清除TX中断信号

    hw_si24r1_write_reg(SI24R1_REG_STATUS, 0x0a);
    int ret = hw_si24r1_read_reg(SI24R1_REG_STATUS);
    if (ret != 0x0a)
        NRF_error |= 0x10; // STATUS bad
    hw_si24r1_write_reg(SI24R1_REG_SETUP_AW, 0x03);
    ret = hw_si24r1_read_reg(SI24R1_REG_SETUP_AW);
    if (ret != 0x03)
        NRF_error |= 0x20; // SETUP_AW bad
    hw_si24r1_write_reg(SI24R1_REG_SETUP_RETR, 0x4c);
    ret = hw_si24r1_read_reg(SI24R1_REG_SETUP_RETR);
    if (ret != 0x4c)
        NRF_error |= 0x40; // SETUP_RETR bad
    return NRF_error;
}
